1. Field of the Invention
The invention relates to a method and apparatus for forming interconnects and other conductive features in the fabrication of integrated circuits and other electronic devices. More particularly, the invention relates to a method and apparatus for forming zero overlap interconnects.
2. Background of the Related Art
Consistent and fairly predictable improvement in integrated circuit design and fabrication has been observed in the last decade. One key to successful improvements is the multilevel interconnect technology which provides the conductive paths between the devices of an integrated circuit (IC) device. The shrinking dimensions of horizontal lines and vertical contacts or vias in very large scale integration (VLSI) and ultra large scale integration (ULSI) technology has increased the importance of forming zero overlap interconnects. Zero overlap refers to the alignment of a line over a plug or a via. In the past, the line width has been greater than the diameter of the contact or via to prevent misalignment between the vias and lines due to distortions in the patterning and etching of the lines. However, with increased circuit density and smaller feature sizes, the need to reduce or eliminate the overlap has become necessary.
FIG. 1 shows a standard aluminum interconnect formed on a substrate over an aluminum metal layer 10. In the process sequence used to from this interconnect, a hole is etched through a dielectric and then filled with a metal to create a conductive path through the dielectric. Metal lines are then formed between filled holes by first depositing a blanket of metal over the dielectric and filled holes and then selectively etching the metal blanket to leave metal lines between the filled holes. The process sequence is performed on a substrate having a metal aluminum layer 10 formed on the substrate and having a low dielectric constant insulator 11, such as silicon oxide, formed thereover. A via 12 is patterned and etched into the dielectric layer to expose the conductive metal layer 10. A liner 13 is deposited conformally in the via and on the field of the low k dielectric layer to provide an adhesive layer as well as a nucleation layer on which tungsten can be deposited using chemical vapor deposition (CVD) to fill the via. Tungsten is deposited as a blanket layer using chemical vapor deposition (CVD) to fill the via and form a blanket layer on the field of the substrate. A chemical mechanical polishing (CMP) process or a tungsten etch back process is then performed to remove the tungsten from the field of the substrate, leaving the via filled with tungsten. An aluminum stack is then formed over the substrate field by first depositing a titanium/titanium nitride liner layer 15 and then depositing a copper doped aluminum layer thereover. The aluminum stack is preferably deposited using physical vapor deposition (PVD) techniques. Next, an antireflective coating (ARC), such as a titanium/titanium nitride layer 17 is deposited over the aluminum stack using PVD. The ARC and aluminum stack are then patterned and etched to leave lines 19 over and between the vias 12 formed below. Typically, reactive ion etching (RIE) is used to etch the aluminum stack and ARC to form the line, which is selective for the aluminum, titanium and titanium nitride. RIE has been shown to perform well with aluminum to define good lines with straight sidewalls. The RIE process used demonstrates a high selectivity for these materials as opposed to tungsten, thereby enabling the tungsten to act as an etch stop for the RIE process.
However, the RIE step used to form the metal line typically has a ten (10) percent non-uniformity factor which requires that the metal stack be over-etched by at least ten (10) percent to insure that all of the metal is removed from the field of the substrate over the dielectric material. Consequently, if the same metal is used for both the via and the line as would be beneficial, a portion of the via may also be etched if misalignment between the line and the via is present, thereby negatively affecting the reliability of the interconnect.
To overcome the limits imposed by the etching requirements and the 10% non-uniformity, the line is typically left wider than the diameter of the via as the RIE process exhibits good selectivity between the line stack and the tungsten which fills the via. This insures that the via will not be etched during the formation of the line because the etch process used to form the line can be selective for aluminum and stop when it reaches the dielectric and/or the tungsten extending therethrough. Because the line in this case is wider than the diameter of the via, any offset due to the patterning process would still result in the line being located over the via. Additionally, the etch process can have a higher selectivity for aluminum compared to tungsten. In such case, if the line were severely offset, the etch process would not intrude into the tungsten via.
With the trend to achieve faster speeds in devices and the demand for increased circuit density, it has become necessary to reduce, and even eliminate, the overlap between the lines and the vias and change the material from tungsten to aluminum and/or copper. Consequently, it has become necessary to provide a process for forming interconnects which can accommodate the use of the same material for both the via and the line and also to accommodate the reduction in overlap between the line and the via.
Therefore, there is a need for a method and apparatus for reliably forming a metal interconnect which can accommodate misalignment between the via and the line.
The present invention generally provides a method and apparatus for forming an interconnect with zero overlap between the line and the via. The invention uses the selectivity of metal etch processes to prevent over-etching into the via during line formation.
In one embodiment, an etch barrier is formed over the filled via to act as an etch barrier when the metal line is etched. In this embodiment, a dielectric layer is patterned and etched to form a via therethrough. Next, a barrier layer is deposited conformally within the via to prevent metal (e.g., aluminum and copper, primarily a concern with copper) diffusion into the surrounding dielectric material. Next, the metal is deposited into the via over the barrier layer and onto the field of the substrate. Preferably, the metal is deposited using a low temperature process such as a combination of CVD followed by PVD or electroplating. Next, the metal is chemically mechanically polished or etched back to remove the metal from the field of the substrate, leaving a metal filled via. Next, an etch barrier layer is deposited over the via to prevent metal diffusion into subsequently deposited dielectric material and to serve as an etch stop during line formation. The etch barrier is preferably formed of a conductive material such as tungsten. Next, a metal stack is deposited over the via and the field of the substrate by first depositing a barrier layer and then a metal layer thereover. Next, an antireflective coating is formed over the upper surface of the metal layer and a line is patterned and etched into the metal stack. An etch process and chemistry having a greater selectivity for the metal in the via as compared to the etch barrier material, e.g., copper to tungsten, is used to etch the line and stop on the barrier.
In another embodiment, the metal deposited on the field of the substrate during via fill is chemically mechanically polished or etched back sufficiently to remove a portion of the metal in the via and form a recess in the upper portion of the via below the upper surface of the dielectric material in which the via is formed. A barrier material is then deposited on the substrate to fill the recess formed over the via and form an etch barrier over the top of the via. The etch barrier is then chemically mechanically polished or etched back to planarize the upper surface of the via with the substrate. Next, the metal stack is formed over the metal via and etch barrier and the line etched therethrough.
In another embodiment, the via is filled with a metal and planarized using CMP or an etchback process. A barrier layer is then formed over the filled via and the field of the substrate. The metal stack is then formed over the barrier layer and the line etched therethrough. An etch sequence is used which is selective first for the ARC layer, then the metal layer and then the barrier layer. By controlling the etch sequence and selectivity of each process, a zero-overlap interconnect can be formed by etching each layer using a different chemistry until the line has been formed over the via.